(1) Field of the Invention
The present invention generally relates to semiconductor integrated storage devices, and more particularly to a dual-port type semiconductor integrated memory circuit.
(2) Description of the Prior Art
There is an increasing need for improvements in the functions and performance of electronic devices. The cost of semiconductor integrated circuit chips has become cheaper and cheaper. As a result, in many cases, a plurality of CPUs (Central Processing Units) are installed in a system in which an entire load of the system is decentralized to the CPUs. In such a system, a dual-port memory is widely used. The dual-port memory has a write port and a read port, and examples thereof are a first-in first-out memory (FIFO) memory and a last-in first-out memory (LIFO).
FIG. 1A is a block diagram of a conventional system having a dual-port memory. As shown in FIG. 1A, a dual-port memory DPM is interposed between two CPUs, labeled CPU.sub.L and CPU.sub.R, and used in common thereto. THe dual-port memory DPM receives address control information and read/write control information from the CPU.sub.L via a control line L1, and sends and reads data to and from the CPU.sub.L via a data bus DB1. Simultaneously, the dual-port memory DPM receives address control information and read/write control information from the CPU.sub.R via a control line L2, and sends and reads data to and from the CPU.sub.R via a data bus DB2. During the above operation, the two CPUs can independently access the dual-port memory DPM without recognizing each other.
The system shown in FIG. 1A is applied to, for example, an instrument. In this case, a peripheral device for use in the instrument is connected to the CPU.sub.L, which receives data from the peripheral device and writes the data into the dual-port memory DPM. A peripheral device used to output the measured data is connected to the CPU.sub.R, which processes the data read out from the dual-port memory DPM and outputs it to the peripheral device. In this manner, the entire process comprising of the measurement process and the output process are shared by the two CPUs, and hence each of the CPUs processes a reduced load at an increased speed.
FIG. 1B is a block diagram of the dual-port memory DPM shown in FIG. 1A. Individual circuits other than a memory cell array 10 are separately provided with a left port and a right port. The left and right ports can independently access the memory cell array 10. An address signal consisting of bits A.sub.0L -A.sub.nL is applied to a left address buffer 31 via the left port, and some of the bits are transferred to a left-row-decoder 21, which selects a specified row. The remaining bits of the address signal are output to a left-column decoder 23, which selects a specified column. In this manner, at least one specified memory cell becomes electrically connected to a left I/O (Input/Output) circuit 25, and thereby data can be written into or read out from the specified memory cell. Control signals /CS.sub.L and /WE.sub.L applied to the left port control a left I/O buffer 33 and thereby data can be written into or read out from the specified memory cell via the left I/O circuit 25. It will be noted that a "/" denotes a low-active signal and corresponds to a "bar" attached above the top of the reference indicating the signal. With respect to the right port, there are provided a right address buffer 32, a right row decoder 22, a right column decoder 24, a right I/O circuit 26 and a right I/O buffer 34, all which operate in the same manner as the corresponding elements in the left port.
In order to establish the above-mentioned independent memory access operations, each memory cell of the dual-port memory DPM is configured as shown in FIG. 1C. Load elements 12 and 13 are made of, for example, high-resistance polysilicon. MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 14 and 15 are cross connected to each other. The four structural elements 12-15 form a flip-flop 11, which stores data in the same manner as in the single-port static memory. In the dual-port memory, two data transfer means are connected to the flip-flop 11. More specifically, one of the two gates of the flip-flop is connected to left-port bit lines BL.sub.L and /BL.sub.L via a pair of transistors 16 and 17 connected to a left-port row select line WL.sub.L. In the same manner as the above, the other gate of the flip-flop is connected to right-port bit BL.sub.R and /BL.sub.R via a pair of transistors 18 and 19 respectively connected to a right-port row select line WL.sub.R. With the above structure, it becomes possible to independently access the memory cell array 10 via the left and right ports.
Generally, in order to transfer data between two devices operating at different bit rates, a rate buffer is provided between the two devices. For example, in order to transfer data processed by the CPU to a printer, a buffer is provided because the bit rate of the CPU is much higher than that of the printer. The buffer temporarily stores data from the CPU, and the stored data is read out therefrom so that the transfer bit rate matches that of the printer. Generally, such a buffer is formed with an FIFO memory.
The FIFO memory is formed as shown in FIG. 1D. The FIFO memory specified by reference numeral 40 comprises of the aforementioned memory cell array 10, a write circuit 41, a write pointer 42, a read circuit 43 and a read pointer 44. A write clock signal /W is input to the write pointer 42, which sequentially generates information indicating the memory cell into which data should be written. That is, the write pointer 42 generates a write address signal in accordance with the write clock signal /W. The write circuit 41 writes input data applied to a terminal Din into the specified memory cell.
A read clock signal /R is input to the read pointer 44, which sequentially generates information showing the memory cell from which data should be read out. That is, the read pointer 44 generates a read address signal in accordance with the read clock signal /R. The read circuit 43 reads data from the memory cell specified by the read pointer 44, and outputs the readout data to a terminal Dout. Reset signals /RST are input to the write pointer 42 and the read pointer 44, which are reset so as to show address "zero" in response to the respective reset signals /RST. Each of the write and read pointers 42 and 44 is formed with a counter, which counts the number of pulses. For example, the write pointer 42 counts the number of pulses contained in the write clock signal /W after it is reset. The read pointer 44 counts the number of pulses contained in the read clock signal /R after it is reset. It will be noted that the read pointer 44 starts to operate after the write pointer 42 starts to operate. With this operation, it is possible to prevent the counter value of the read pointer 44 from exceeding that of the write pointer 42.
A description will now be given, with reference to FIG. 2A, of the write operation of the dual-port memory DPM. In FIG. 2A, parts which are the same as those shown in FIGS. 1A through 1D are given the same reference numerals. Load transistors 51-54 are connected to pairs of bit lines BL and /BL in the respective ports (BL.sub.L, /BL.sub.L ; BL.sub.R, BL.sub.R), and maintain these bit lines at a predetermined level. Load transistors 59-62 are connected to the pairs of data lines DB and /DB in the respective ports (DB.sub.L, /DB.sub.L ; DB.sub.R, /DB.sub.R), and maintain these data lines at a predetermined level. Transistors 55-58 for use in column selection are interposed between the pairs of bit lines BL and /BL and the pairs of data lines DB and DB in the respective ports. The transistors 55 and 56 are controlled by a column select signal Y.sub.L, and the transistors 57 and 58 are controlled by a column select line Y.sub.R. Sense amplifiers (not shown in FIG. 2A for the sake of simplicity) in the read circuit 43 are connected to the respective pairs of data lines, and sense the differences between the respective pairs of data lines. The write circuit 42 is connected to the data lines, and controls the write operation in the memory cells. In order to explain the write operation via the right port with reference to FIG. 2A, only a related write circuit part (comprising of transistors 63-66) is shown in FIG. 2A.
It will now be assumed in FIG. 2A that data "H" is written into a selected cell via the right port and the left port does not select a row on which the write operation is being carried out. That is, a "H"-level signal is applied to the word line WL.sub.R, and a "L"-level signal is applied to the word line WL.sub.L. In order to write ("H" representing a high output) into the selected cell, "H" is applied to an input node IN.sub.R, and ("L" representing a low output) is applied to an input node /IN.sub.R. At this time, the transistors 63 and 66 of the write circuit are ON, and the transistors 64 and 65 thereof are OFF. Hence, the level of the data line DB.sub.R switches to "H", and the level of the data line /DB.sub.R switches to "L". The respective levels of the data lines DB.sub.R and /DB.sub.R are transferred to the bit lines BL.sub.R and /BL.sub.R via the transistors 57 and 58, respectively, and hence the levels of the bit lines BL.sub.R and /BL.sub.R switch to "H" and "L", respectively. Hence, a node C of the memory cell 11 switches to "H" and a node /C thereof switches to "L", so that the transistors 15 and 14 are turned ON and OFF, respectively. In this manner, data "H" is written into the memory cell 11. In this state, the level of the bit line /BL.sub.R when it is switched to "L" is a floating level with respect to the ground level due to load currents I1 and I2 from the transistors 54 and 62, respectively. However, there is a slight difference between the floating level and the ground level because normally the transconductance values gm of the load transistors 54 and 62 are set to be smaller than that of the transistor 66 for use in data writing. Generally, such a slight difference is equal to hundreds of millivolts. During the data write operation, the floating level is written into the node /C of the cell via the transfer transistor 19. This floating level is a level which is enough to turn OFF the other cross-coupled transistor 14. Hence, a stable write operation can be carried out.
In the case where the right and left ports select the different rows, data is written into the dual-port memory in the same manner as in the case of the single-port memory. This means that a special problem does not occur. However, a problem will take place if the right and left ports select the same row. This problem will be described below with reference to FIG. 2B.
The operation executed when the same rows are selected via the right and left ports is different from the operation executed when the different rows are selected in that the row select line WL.sub.L in the left port is maintained at the "H" level. Hence, a current is generated which flows from the load transistor 52 connected to the bit line /BL.sub.L of the left port to the node /C of the memory cell via the transfer transistor 17 of the left port. If the right and left ports select not only the same row but also the same column, the column select transistor 56 of the left port is ON, and hence a current flows from the load transistor 60 of the left port to the node /C of the memory cell. The above-mentioned currents flowing to the node /C of the memory cell from the left port are absorbed, through the transfer transistor 19 of the right port and the column select transistor 58 of the right port, by the transistor 66 which is a structural element of the right-port write circuit. In this manner, the transistor 66 of the write circuit must absorb a larger amount of load current when the same column and the same row are selected by the left and right ports. Further, the level of the node /C of the memory cell is a level obtained by dividing the difference between the levels of the bit lines /BL.sub.L and /BL.sub.R by the ratio of the transconductance values of the transistors 17 and 19. Generally, the transistor 17 has the same channel length and channel width as those of the transistor 19. Hence, the level of the node /C is high with respect to the ground level, being equal to, for example, 1.5 V. This level of the node /C does not make the transistor 14 turn OFF, and hence the write operation is unstable.